Electronic systems, such as microprocessor based computers, typically operate on data that is stored in electronic form in a memory device. The memory device stores the data at specified voltage levels in an array of cells. Conventionally, the voltage levels represent that the data is either a logical “1” or a logical “0.” In dynamic random access memory (DRAM) devices, for example, the cells store the data as a charge on a capacitor. When the data is read from the memory device, sense amplifiers detect the level of charge stored on a particular capacitor so as to produce a logical “1” or a logical “0” output based on the stored charge.
As the size of memory devices decreases, the capacitor in each cell covers a smaller surface area or footprint on the substrate, chip or wafer. If the structure of the capacitor is left unchanged, these smaller capacitors cannot store as much charge because the storage capacity of a typical capacitor is proportional to the size of its storage electrodes. Unfortunately, at some point, the capacitors become too small to store sufficient charge and sense amplifiers in the memory device are unable to differentiate between charge due to noise and the charge due to data stored in the cell. This can lead to errors in the output of a memory device making the memory device useless in the electronic system.
Conventionally, memory manufacturers have used one of two types of capacitors in DRAM devices. First, many manufacturers use “stacked” capacitors to store data for the memory cell. Stacked capacitors are typically formed from polysilicon and are positioned above the conventional working surface of the semiconductor chip or wafer on which the memory device is formed. A contact couples the capacitor to a transistor in the memory cell. Some manufacturers use “trench” capacitors instead of stacked capacitors. Trench capacitors are typically formed in a trench in the semiconductor wafer or chip. The trench is filled with polysilicon that acts as one plate of the capacitor. In this case, the semiconductor wafer or chip acts as the second plate of the capacitor.
Designers have experimented with various configurations of capacitors, both stacked and trench, to maintain the capacitance as the footprint available for the capacitor decreases. In the area of stacked capacitors, designers have used texturization, stacked V-shaped plates and other shaped plates to increase the surface area of the plates without increasing the footprint of the capacitor. For example, designers have developed techniques to produce hemispherical grains on the surface of one polysilicon plate of the stacked capacitor. This roughly doubles the storage capacity of the capacitor. Researchers have also described techniques for further increasing the surface area of the polysilicon plate, and thus the storage capacity of the capacitor, by using phosphoric acid to create pores in the polysilicon plate. See, Watanabe, A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMs, Symposium on VLSI Technology, pp. 17-18, 1993. These micro-roughened polysilicon surface features have sizes of the order 100A or 10 nm. With this technique, it is claimed that a 3.4 times increase in capacitance can be achieved.
One problem with the use of stacked capacitors is their positioning above the surface of the substrate. This positioning can interfere with the proper functioning of the equipment used to fabricate other parts of a larger circuit.
Conventionally, as the footprint available for trench capacitors has decreased, the manufacturers have used deeper trenches to maintain sufficient storage capacity of the trench capacitor. IBM has developed another technique in an attempt to maintain sufficient storage capacity as the footprint of the trench capacitor decreases. This technique uses an anodic etch to create pores in the single crystalline silicon in the trench of the trench capacitor. See, U.S. Pat. No. 5,508,542 (the '542 patent). One problem with this technique is the lack of control over the distribution of the pores in the surface of the single crystalline silicon. Thus, the '542 patent does not provide a technique that can be used reliably for large scale production of memory devices.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a realizable trench capacitor with increased surface area compared to prior art capacitors for use in high-density circuits such as dynamic random access memories.